This invention relates to a voltage follower circuit.
FIG. 1 shows the schematic arrangement of a prior art voltage follower circuit. This voltage follower circuit includes npn transistors TR1, TR2 whose emitters are grounded through a constant current source 1, a pnp transistor TR3 whose collector and base are connected to the collector of the npn transistor TR1 and whose emitter is connected to a power supply terminal V.sub.CC, a pnp transistor TR4 whose base is connected to the base of the pnp transistor TR3, whose collector is connected to the collector of the npn transistor TR2, and whose emitter is connected to the power supply terminal V.sub.CC, and an npn transistor TR5 whose base is connected to the collector of the npn transistor TR2, whose collector is connected to the power supply terminal V.sub.CC and whose emitter is connected to the base of the npn transistor TR2 and also grounded through a constant current source 2. The base of the transistor TR1 is connected to an input terminal V.sub.in. The base of the transistor TR2 is connected to an output terminal V.sub.out.
Where, with the above-mentioned prior art voltage follower circuit, an output voltage, that is, the base voltage of the transistor TR2 runs higher than an input voltage, that is, the base voltage of the transistor TR1, then a large current runs through the collector TR2. As a result, the base potential and consequently emitter potential of the transistor TR5 falls, causing the base potential of the transistor TR2 to drop and also an output voltage from the transistor TR2 to approach an input voltage.
Conversely where an output voltage becomes lower than an input voltage, then the collector current of the transistor TR2 drops to raise the base potential of the transistor TR5, leading to a rise in the emitter potential of the transistor TR5 and also in an output voltage.
The prior art voltage follower circuit of FIG. 1 has a simple arrangement and has the advantage that a difference between the input and output voltages, that is, offset voltage is low. However, this prior art voltage follower circuit has the drawback that since the transistors TR1, TR2 are designed to have a large gain in order to reduce the offset voltage, an oscillation tends to occur in this circuit. To suppress the oscillation, therefore, a resistor 3 is connected, as shown in FIG. 1, between the base of the transistor TR2 and the emitter of the transistor TR5, and a capacitor 4 is provided between the base and collector of the transistor TR2. However, formation of the capacitor 4 unavoidably enlarges the area of a required chip, giving rise to difficulties in integrating such voltage follower circuit.